Hit time + Miss Rate x Miss Penalty.
There are 3 properties we have to try to balance.
Spacial locality:
If you access one location, odds are you're going to access its neighbors sometime too.
Temporal locallity:
If you access sometihng, odds are you're going to access it again sooner rather than later.
We don't have to store in memory everything that the code wants to execute. We just have to make sure that we have the “right things” in memory at the relevant point in time.
Cache design questions:
Block placement:
• Remeber direct mapping: certain slots in memory could only map to certain slots in cache. What was that good for?
◇ This improves hit time. There is no search. Certain memory locations can only be mapped to specific cache slots. The cache slots are a function of the address.
◇ Direct mapping is always closest to the registers because we want the minimum possible hit time in the registers
• Remember associative mapping:
◇ “Full associativity”
◇ says that ‘i can map any slot from MM into any slot in cache.’ What is that good for?
◇ This minimizes miss rate because it gives you most flexibiity.
• In the direct case, because certain slots in MM can only appear in a given slot in cache, if you need to access several memory lcoations that happen to map to the same cache spot, you lose a lot of efficiency when they are constantly overwriting one another. Associative mapping allows you to take advantage of temporal locality and put the two values in different cache blocks.
• Hit time: direct mapping
• Miss rate: full associative
• We can try to blend the two: set associative
◇ split the cache into two sets and try to make use of both strategies.
• associative mapping... don't know right away if you have a hit or a miss. have to search the entire cache.
Block identification
• umm
Block replacement
• How do you target a block for replacement. Model of Least Frequently Used
Write strategy
• About synchronization when you perform a write, because you write to the cache.
• Write throgh: write through multiple levels of cache/mem to make sure they're in sync
• write back: write to the lowest level of memory and mark it as dirty. When you go to replace a dirty cache slot you have to make sure it gets pushed back to the next level of memory because it currently holds more recent information
• write buffer: write to the write buffer, and then in the background the write buffer can perform all the writes.
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