Scoreboards

2023/06/07 - 16:24

Has an Issue stage, a Read Operand stage, and writeback

Scoreboard: place where we keep all the infomration we need to orchestrate everything. We have fetch and decode, then two sets of tests we need to apply.
Issue:
- Where we test the destination general purpose register. So that;s gonna be a write after write hazard. As logn as there/s no insrtuction with the same destination, when we;'ll release from issue.

Read oeprand:
- where we test for read after write hazard. no issued active instruction is allowed to write operands to pending instruction operands

Execution
- here is where we release operands (both) and that's different from tomasulo becuase tomasulo would try to grab an operands as soon as it was useful, and sit there with its register renaming in order to figure out which execution station was gonna produce something,. now were trying to centralize all these tests.

Write GPR
- lets us stall after execution
- enforces WAR tests.

centralization: every clock cycle, when an instruction appears you have to test for all hazards. You don't have a data structure that figures that out for you. Here, given the instruction we release and the incoming instruction, we test for all the hazards. We only release one section to another if it passes the first one.
If it passes the first two then you can go ahead and execute

But there's still one hazard mising: write after read.
We dont want the execution writing to someting before other instructions have the opportunity to read it. that's the last test. The stall cycle is introduced by the scoreboard, to prevent WAR.

Fields:
- Busy
- Op
- F(i)
- its gone

Consider the following piece of code: * RAW . WAW $ WAR

F6*. ← Mem[34 + R2]
F2**** ← Mem[45 + R3]
F0** ← F2**** x F4
F8*** ← F6*$ - F2****
F10 ← F0** + F6*$
F6.$ ← F8*** + F2****

“I like pretty pictures”

	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23
F6 ← M[R2 + 34]	F	D	I	R	E	M	W
F2 ← M[R3 + 45]		F	D	I	R	E	M	W
F0 ← F2 x F4			F	D	I	R	-	-	M1	2	3	4	5	6	7	8	9	10	W	<-- no mem stage
F8 ← F6 - F2				F	D	I	R	-	A1	A2	W
F10 ← F0 / F6					F	D	I	R	-	-	-	-	-	-	-	-	-	-	-	D1	......	D40	W
F6 ← F8 + F2						F	D	I	R	-	-	A1	A2	-	-	-	-	--	-		W
											Theres 2 things going on. Because we have to stall when we spot the hazard.

Index