FIELDS:
- ID : link up the targets
- Busy
- Vj : known source
- Vj
- Oj : unknown source
- Ok
- A
Slice through clock cycle 6 from the table:
What happens when we go to clock cycle 7?
We assumed that the execution stations are pipelined
This means that we can have parallel add (for example) instructions as lo9ng as they don't start in the same cycle.
The compiler doesn't know how lng it might take to resolve accesses to memory.
Boils down to tricks with relabelling dependencies. As soon as the relevant dependency is available, you grab it. If something is unkown, then you can look up the label that you are waiting for. We just have to do a lookup in our target register table to find out which labels are being executed.
In order to implement this , we test this data structure a lot.
Modern CPUs use multi issue. What does this mean?
Fetching more than one instruction.
Speculative execution: On a branch instruction, make a prediction and execute down that path. The clinch being you are executing down that path before knowing the branch resolution, meaning the machine needs to be able to undo things, because at some point you will predict the wrong thing and need to undo it.
Virtual memory: From the application's POV, everything is logically addressed. It's like starting from address 0 and going upwarsd. from a hardware POV, different applications/threads are mapped to different regions of memory. Otherwise they would clash/overwrite each other.
What other properties would you want to implement in virtual memory so things remain separate?
idk i zoned out
Tomasulo's has some hardware overhead due to additional buses and whatever
There is still the bottleneck of the Common Data Bus, because at the end of the day only one thing can be written to the bus at a time.
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