2023/05/10
What do we have?
- a pipeline
→ fetch decode execute memory writeback
→ where are we fetching from?
⇒ PC
⇒ fetching from instruction memory
⇒ where to we put it?
• instruction register
→ decode:
⇒ does this need instruction memory?
• no because our instruction is in the IR
• everything is relative to that instruction until we stop execution
• what do we do the the PC?
◇ add 4, point to the next sequential instruction
◇ call this the NPC (next program counter)
⇒ push values into register A, B, Immediate (possibly) depending on the instruction
→ execute
⇒ need NPC, IR
⇒ might need A,B and/or Imm
⇒ put result of ALU comp in ALU out
⇒ set flag: condition
→ memory
⇒ need NPC and IR
⇒ no longer need A. Might need B if you need to store something.
⇒ need ALUout (might consume the result during this cycle)
⇒ condition operates the multiplexor
→ writeback
⇒ update the state of the machine in such a way that the ISA can see the result
⇒ update GPR
⇒ (read the GPR in decode)
Index