RRC
- oldcarry ← carry bit
- carry bit ← lsbit of register
- shift register right
- MSbit reg ← oldcarry
emulator should have ability to change memory stored at a given location and change contents of a register.
ALu stuff from last class:
- Why would you want a case where output matches input?
→ Copying a register to another e.g. LR ← PC
- bit slicing: taking a string of ALUs and stringing them together. e.g. 4 4-bit alus make a 16 bit one.
- a CPU maintains a register indicating the result of last arithmetic or logical operation
→ PSW, FLAGS register, Condition code regsiter....
PSW
Priorities:
- priorities 0-7
- 0: lowest, 7: highest
- we have to remember the previous priority
- once you've finished at one level with an exception, what we allow is, we have our application (running at say, 3) and a device at 4, the device interrupts and enters its Interrupt Service Routine. If another device interrupts at 6, control passes to the ISR of that device.
- To know where to return to, we keep the previous priority.
- The psw, unlike making a subroutine call, has to be saved for an interrupt.
Zero and Negative
- psw.z is 1 if the result of the previous operation is 0. it is 0 otherwise
- psw.n gets the msb of the result of the operation.
CEX
- CEX <cond> <true count> <false count>
- cond: EQ, NE, MI, PL
- true count: # to execute if the condition is true, number to skip if the condition is false
- false count: # to execute if the condition is false, # to skip if the condition is true
Detecting sign of src = sign of dst: complement of an XOR of the sign bits
detecting if sign of src != sign of dst: XOr the sign bits
Exceptions
How can we communicate iwth devices?
- polling
→ device undergoes a status change
- exceptions
→ priority
- interrupts
→ device undergoes a status change
→ increasing cpu throughout
→ interrupt controllers
⇒ if we have all kinds of devices trying to interrupt we need to prioritize somehow
→ why do we have interrupts? to avoid having to ask all the time. CPU can be doing other things and only be interrupted when a status change occurs. This increases CPU throughput.
- faults
→ segmentation and paging
→ when does a fault occur? during the execution cycle (fetch decode execute), the cpu enters an unknown state
→ as opposed to an interrupt, which occurs after the execution cycle has completed
→ paging fault could occur during a fetch, when the page needed is not in memory.
→ invalid instructions can cause a fault in the decode section
→ fetch could have an illegal address
→ page faults could happen during memory access in the execute phase
→ divde by zero can happen in execute phase
- traps
→ voluntary preemption
→ trap occurs once the instruction is finished.
Generic device
- has data (read/write), control (program the device) and status.
- devices have registers to allow program to access
Memory-mapped devices
- devices are associated with memory addresses
- memory and devices have address decoders
- access device registers using memory access commands Load and Store.
Can also have device memory. Access requires specific instructions IN and OUT. Bus has additional channel to indicate device memory is being accessed
XM23 Devices
- consists of 2 bytes
- 6 fields of interest
→ control-status register
⇒ [Reserved][ENA][OF][DBA][I/O][IE]
⇒ 0: IE: Interrupt Enable (CTRL)
⇒ 1: IO: i/o Input device or output device (CTRL)
⇒ 2: DBA (STAT)
• Data byte available (keyboard)
• Data buffer available (screen)
⇒ 3: OF: Overflow
⇒ 4: ENA: Enable device
→ data register
- Device memory is low memory. (8bits) and the following 8 bits are control
- 3 built in devices in xm23, CLK, KB, SCR
- device polling
→ kb input:
→ READ kbcsr INTO csr
→ WHILE csr.DBA = 0 DO
⇒ ......... look at the slides ig
Index