The Fundamentals of Pipelined Processors

- RISC-V : open source ISA
→ in risc-v: GPR labelled a0, a1...
- Logic propagation time
→ these components involve a lot of gates
→ in one clock cycle, data would have to go through the decode and the alu...
→ each gate has a small propagation delay, which compound.
- To speed it up, we can split each thing such that we only do part of the work at once.
→ doing less on each cycle
→ 1st cycle: fetch 2nd: decode while u fetch the next thing, 3rd: execute while decoding from 2, and fetching again
- Frontend pipeline
→ plans the code the backend will execute
→ goal is to keep the backend as busy as possible
→ 1) fetch and decode
→ OR
→ 1) fetch 2) decode
- backend pipelie
→ actually executes the instructions... writes to memory etc
→ 2) execute and writeback
→ OR
→ 3) execute 4) writeback
→ OR
→ 3) execute 4) memory 5) writeback
- ayo he mentioned the intel atom (the processor this thing uses)

Pipeline Hazards

- Control hazard
→ need a result of conditional before its ready
- Structural hazard
→ need the same resource for two instructions
- Data hazard
→ instruction needs result of an instruction that's not finished executing.

Pipeline stalls:
- waiting for resources

Branching:

neorv32 ← look up

webriscv

Index