2023/05/30 - 12:27
- ADD:
→ DST ← DST + SRC
- If we add the source to the destination, we get a result. We also can get a carry
- Can we do 32 bit arithmetic on this machine?
→ yes. How?
→ Split the numbers in to their higher and lower words.
→ SRC = s1, s2
→ DST = d1, d2
→ RES = r1, r2
→ ADD S1 D1
→ Carry?
→ ADDC S2 D2
- Which half holds the sign?
→ The MSB. aka the 32nd bit
→ Located in D2
- Add = D ← D + S
- AddC = D ← D + S + PSW.C
1234: SRC64 Word LowWord
Word HiWord
- we can also do 64 bit arithmetic in a similar way
- MOVL SRC64, R0
- MOVH SRC64, R0
- If SRC64 is stored at location 1234, then that value is now stored in R0
- ;R0 = #1234
- LD R0, R1; R1 ← LowWord
SUB instruction:
- D ← D - S
- We do this with complements
- D ← D + ~S + 1
- ~S = ones complement of source
- This operation can still result in a carry
- If we want to do 32 bit subtraction:
→ Take LowWord (complement + 1) + destination (low word) to get the low result
→ Take High word of source (complement + 1 ) + destination (hi word) + carry bit to get the high result
- SUB: D ← D + ~S + 1
- SUBC: D ← D + ~S + PSW.C
We can replace these four functions with a functions that takes the same things as arguments
add_func(dst, Src, Carry, w/b)
if wb = word then
res ← dst + src + carry
else
res ← dst.b + src.b + carry
update the psw(res, dst, src, w/b)
Then for sub, call add_func(d, ~s, psw.c)
Compare is also similar
cmp: dst - src.
We could call the add_func() we made.
add_func(dst, ~src, 1)
this would change the psw.
assuming the add_func returns the value, in the case of compare we would ignore it.
DADD:
- most microprocessors let you do BCD (binary coded decimal) arithmetic
- If we have a byte, we can split it into two nibbles.
- The only legal patterns are 0-9 (0000 - 1001)
- we have to reinforce this in our emulator
- We can also get what is referred to as a half carry, when a carry occurs from the lo nibble to the hi nibble
- When we add two nibbles together, we get another nibble. each nibble can be 0-9, so the result can be 0-18, but 18 doesnt fit in a nibble.
- RES ← N1 + N2
- if the reuslt is 0-9, when we know we are okay
- if the result is 10-18 then there's a problem
- if RES > 9, then RES ← RES - 10
- HC (half carry) ← 1
- the HC would need to be added to the equiation when calculating the hi nibble
- that operation can also result in a half carry.
- The initial half carry is 0.
DADD_func(d, s, HC)
res ← dest + src + hc
if res > 9,
res -= 10
hc = 1
else hc = 0
We can use a union to handle the carrys
struct nibbles{
unsigned n0:4
unsigned n1:4
unsigned n2:4
unsigned n3:4
unsigned nibs[4]:4;
}
union BCD_NUM{
unsigned short word;
struct nibbles nib;
}
DST/16 bit
union bcd_num d1;
d1.word = DST
d1.nib.n0 ← ....
PSW:
- A running program has state
→ global vars
→ stack vars
→ current statement being executed
- supported by internal machine state:
→ PC
→ SP
→ LR
PSw is an internal CPU register (like the IR)
[previous priority][xxxx][FLT][current priority][V][SLP][N][Z][C]
FLT = fault.
We can define this in C
struct PSW{
unsigned c:1, z:1, n:1.....
}
SLP:
1: cpu is in a low power sleep state and not executing
it can be awakened when an interrupt occurs
0: cpu is awake, executing
FLT:
1: CPU has experienced a systems fault
0: cPU is not in the fault state
There are 3 types of exceptions:
1. Interrupts - control passes to devices. application is running... Interrupt service register gets an interrupt... control passed to devices
2. Traps - The application is running...you run into a trap (instruction)... control passes to a higher priority (e.g OS)
3. Fault - CPU enters an undefined state. e.g. devide by 0, page fault, illegal instruction (opcode unrecognized), invalid address(PC is odd), ...
The fault bit should be set because if the fault handler encounters fault then you end up with a double fault, and in that case the machine has to stop.
Priority:
- Applications run at 2 priorities: 0 - lowest or 7- highest
- Higher priority application can interrupt a lower priority application
- when an interrupt finishes, the next highest priority application begins execution.
Index