Fetch
- bus function:
→ args: PC, &IR, RD, Word
→ PC = PC + 2
→ IR is a hidden register, unsigned short
- bus
→ void bus(unsigned short MAR, unsigned short * MBR, r/w, w/b)
→ read: mem[mar] = *mbr
→ write: *mbr = mem[mar]
Decode
Instruction: [opcode] [operands]
- how do we access them?
→ ADD_BIS{
⇒ unsigned short dst:3, src:3, wb:1, rc:1
→ }
→ You can also use bit masking
→ #define DST(x) (x & 0x07)
→ #define SRC(x) ((x>>3) & 0x07)
→ #define WB(x) ((x >> 6) &0x01)
→ #define RC(x) ((x >> 7) & 0x01)
- INST
→ dst = regfile[0][DST(inst)]
→ src = regfile[RC(inst)][SRC(inst)
→ IF WB(inst) = BYTE THEN
⇒ byte operations
→ ELSE
⇒ word operations
Word or Byte?
- WB(instr) gives us 0 (word) or 1 (byte)
- If it's word, the arithmetic is on the entire 16 bits.
- if it's byte, it only operates on the LEAST significant half of the word.
- The register file is stored as 16 bit values (shorts)
- We can create a union to allow byte operations
- union word-byte{
unsigned short word
unsigned char byte[2]
- }
- union word-byte dst, src
→ dst.word
→ dst.byte[0]
→ dst.word = regfile[0][DST(inst)]
→ WORD add:
⇒ dst.word = dst.word + src.word
→ BYTE add:
⇒ dst.byte[0] = dist.byte[0] + src.byte[0]
PSW
- what bits are we looking at?
→ if we're doing word operations, the MSB (15)
→ if we're doing byte operations, bit 7
- psw(dst.word, src.word, res.word)
- V
- N - gets the MSB
- Z - if byte operations, look at the LSB, otherwise look at the entire word.
→ if word then z ← res = 0
→ else z ← result & 0x00FF
- C - gets CARRY[msS][msD][msR]
- V - gets OVERFLOW[msS][msD][msR]
Where does the PSW exist?
struct psw.bits{
unsigned short c:1;
unsigned short z:1;
unsigned short SLP:1;
unsigned short n:1;
unsigned short v:1;
}
struct psw.bits psw;
Index