Memory
- can be classified into primary and secondary
→ a program has to be in primary to be run.
→ primary: directly accesible by CPU
→ secondary: accessible through a device.
- Memory is measured in:
→ Kibibyte (KiB) = 1024 bytes
→ mebibyte (MiB) = 1024 KiB or 1048576 bytes
→ gibibytes (GiB) = 1024 MiB or 1073741824 bytes
- contents of each location can hold
→ v
- Princeton or Von Neumann memory:
→ instruction and data coexist in memory
- Harvard
→ Small programs could fit in instruction memory
→ would have two buses, one for intruction and one for data
→ two separate memories for instruction and data
- How are multiple byte structures stores?
→ short: 0x1234
⇒ MS byte is 0x12 , LS byte is 0x34
→ This can be stored in different ways depending on the machine.
→ Little Endian: store LS byte first
⇒ (intel, others use this)
⇒ 1000: 0x34
⇒ 1001: 0x12
→ Big Endian: MS byte first
⇒ (network byte ording)
⇒ 1000: 0x12
⇒ 1001: 0x34
- Applicable to all multiple-byte structures, signed and unsgned
The CPU
- memory contains the instructions and data.
- the CPU interprets and executes the instrucitons.
- what the CPU does:
→ MDR: Memory data register.
→ MAR:
→ MDR and MAR are connected to primary memory.
→ addresses only go from the CPU to memory through the Memory Address register
→ the data register is bidirectional, can read or write.
→ Instruction or data come into the MDR, addresses go to primary memory through MAR
→ the control register (connected to MAR) specifies read or write.
→ Most instructions consist of Opcode and Operands
⇒ opcode telsl CPU waht to do, Operands what to operate on.
→ Control unit decides which registers need to be accessed.
→ 3 phases of the instruction system
⇒ fetch
⇒ decode
⇒ execute
→ PC stores the address of the next instruction to execute
→ SP points to the top of the stack.
⇒ accessing memory is expensive.
⇒ have to put the address out, specify read or write, get the response. takes time.
⇒ Makes more sense to have a s much data as you can inside your registers, because the cost of accessing a register is virtually none.
FETCH
- can increment the program counter while the cpu is waiting for a memory fetch, by performing a constant add (by the instruction size) within the CPU
- Fetch an instruction from a memory location
DECODE
- extract opcode and operands
- determine required actions
in the XM23 table 25
- bits on the left side are the opcodes
- they are all unique.
EXECUTE
- executes it lol
The instruction cycle
- 3 types of exceptions
→ Interrupts (device)
→ Faults (CPU)
⇒ page fault
⇒ CPU can't perform its task.
⇒ best example is divide by 0.
→ Traps (software generated)
⇒ SVC (service call)
⇒ INT (on intel)
⇒ passes control to the OS to perform a task
What the bus does
- connects CPU to memory, and to devices
- devices communicate to the bus which connects to the CPU
- carries
→ Address lines (cPU to memory/devices)
→ data lines (bidirectional)
→ control lines (read or write)
All devices have the same generic format.
- without a device, the machine can't communicate to the outside world.
- what about the loader?
→ It's an piece of software reading from an external device.
- devices have registers to allow a proogram to access the device.
→ not the same as CPU registers
- We can read/write data (depending on the device)
- we can control/program the device.
→ parity bit... etc
- the device has a status, this tells us the state of the device
→ overrun error: occurs when the CPU can't read the data fast enough and it gets overwritten
Memory mapped devices:
- devices are associateed with memory addresses
- memory and devices have address decoders
- they access device registers using mem commands like LOAD, STORE
Device Memory
- a signal is sent from the CPU to the device memory (saying i want to read or write) and the device memory pushes it on to whichever device is specified.
- Accesseing device registers requires special instructions, e.g. In/Out
- Bus has additional channel to indicate that device memory is being accessed
Index