XM-23 ISA
- there is no single definition of what an ISA is
- some of them:
→ programmers view of the CPU
→ abstract model of the computer and its CPU
→ boundary between softwre and hardware
→ basic instructions undertsood by the processor - the istruction set
→ how data and code structures are supported by the cpu
→ the ISA is the instruction set plus the CPU
Overview of XM23
- 16 bit microprocsesser
- load-store RISC
→ reduced instruction set computer
⇒ can define your own stack, but theres no push or pull
⇒ no return instruction
⇒ which pointer would you want to adjust if you're messing with the stack?
• stack pointer
⇒ has to be way to modify SP
- CPU has 8 registers
→ 5 GPR
⇒ r0-r4
⇒ leftmost bit is MSB (bit 15)
⇒ 2 bytes
→ link reg
→ stack pointer
→ PC
- 41 Fixed-length instructions
- orthogonal ISA
→ any operation we can perform on one register, we can perform on any other.
→ this can be problematic if you blindly alter a special purpose register, such as PC, which can cause problems
- 5 addressing modes
→ register (one or two)
→ imeediate
→ direct
→ indexed
→ relative
- 8 built in constants
→ -1, 0, 1, 2, 4, 8, 16, 32
→ size of common data types and common operations
→ all arithmetic ops have to be register-register
→ ADD r0 r1 ; R0 ← r0 + r1
→ ADD #1, R1
→ ADD #0 R1
- conditional bracnhes
- 16-bit system bus
- memory:
→ 64 KiB (64 kibibytes)
→ byte and word addressable
→ little endian
→ 0x1234 → 1000: 34
1001: 12
→ insttructions and data share memory (von neumann)
- 3 types of exception
→ interrupts
→ fault (divide by 0... page fault)
→ traps
→ stores PC and status
- up to 8 memory-mapped devices
→ kbr, screen, clock
- 8 priority levels
→ pecking order. higher priority get done first
- reduced exception overheads
- can be implemented as von neumann or harvard
- can be von neumann or pipelined CPU architecture
Memory:
- bytes: 8 bits
- byte addressable
- byte address: 0000 to FFFF (2^16 addreses)
- 64 KiB (65536 bytes)
- word: 16 bits (2 bytes)
- word addressable
- if u wanna access a word it has to land on an even byte boundary.
- word address == byte address >> 1
- 32768 words
- devices have 3 registers
→ control
→ status
→ data
- low memory reserved for devices (mem mapped)
→ when you have a device there will be some bytes reserved for control bits
⇒ stop/start etc
→ the device will have a section to read or write data
→ status gives the status of the device
⇒ whether character received/transmitted
⇒ whether an error occured (e.g. overrun)
→ we have to UARTs, one is transmitting and one receiving
⇒ line idles in the mark space
⇒ if the transmitter wants to send char, it will send a space (low signal) to indicate the start of the frame
• “start bit”
• followed by data bits (coould be marks or spaces / 0 or 1)
• parity bit follows
• followed by idle period, no transmission. signals the end. can be 1, 1.5 or 2 bits long can be 1.5 because of time.
• why? keyword is asynchronous
• hardware can stay in sync for 1 character. once the frame ends theres no guarantee that theyrs still in sync.
• both ends have shift registers. receiver copies it into its receive buffer.
- interrupt vectors
- when you have an interrupt, the psw (program status word) has the priority. (process priority) this determines whether the interrupt is received
- other word is the address of the ISR (exception handler's entry point)
- high memory reserved for interrupt vectors
- svc tracks
- cant trap from 6 down to 4. can only trap upwards. because the exception handler would have access to the higher priority memory which it shouldnt.
Register set
- 8 16-bit registers
- BP gives us access to the stack frame. used for function calls
- in a stack frame:
→ hi memory
→ parameters
→ return add
→ old BP (BP points here)
→ Autos (SP points to top of this)
⇒ func(a,b,c)
int x,y,z
⇒ parameters are a, b, c
⇒ autos are x ,y, z
⇒ autos are “locals”
⇒ if we say x = a, BP -2 lets us acces x, bp +2 +4 lets us access a (in param section)
⇒ BP allows us to reference parts of the stack frame
→ lo memory
- 5 general purpose
→ registers r0-r4
→ arithmetic and logic
→ addressing
→ word or byte accessible
- 3 special purpsoe
→ r5 link register
→ r6 stack pointer
→ r7 program counter
- constants are stored in the register file
→ easy access, fast
General purpose registers
- 16-bit long 0000 - FFFF
- used in arithmetic and logic operations
- 0 or 16 bit signed/unsigned arithmetic
Link register
- 3 possible uses
→ return addresses in subroutine calls
⇒ must be word(even byte) address
⇒ call: LR ← PC
⇒ return: PC ← LR
⇒ LSB must be 0
→ indication exception occured
⇒ LSB is 1
→ as a general purpsoe register
⇒ LR should be stacked before using
⇒ if LR gets overwritten without being stored, return address is lost.
Stack Pointer
- current top of stack
- must be word (even byte) address
- pull:
→ 1. Data ← mem[SP]
→ 2. SP ← SP + 2
- push:
→ 1. SP ← SP -2
→ 2. Mem[SP] ← Data
Program Counter
- address of next instruction to execute
- must be even byte address
- sequential operations:
→ PC ← PC + 2
- change flow-of-control (branch, subroutine, exception)
→ PC ← new effective address
Program state
- global vars
- stack vars (autos)
- current stmt being executed
- supported by internal machine state:
→ PC, SP, LR, registers, execution state (fetch, decode...)
Program status word
- indicates current cpu state
- internal cpu register where:
→ c: carry
→ z: zero
→ n: negative
→ V: overflow (signed arithmetic)
→ slp: cpu is in sleep state
⇒ can't sleep at the highest priority, because you sleep until a higher priority interrupt occurs and if uralready at the highest you will sleep forever.
→ flt: cpu fault has occurred
⇒ if you have a fault, you cant have another one. if your fault hadnler has a fault, youre doomed
⇒ double faults will be detected
→ priority
Instruction set:
- fixed length 16-bit instructions
→ arith/logic
→ branching/tranfer control
→ memory access (load/store)
→ zer0, one, and two address instructions
- most instructions work with registers
- 8 or 16 bit load/store mahine
→ 4 memory access instructions
→ 16 bit addresses
→ 3 access methods (direct, indexed, relative)
How to implement register file in assignment
- table of possible registers 0-7, corresponding constants
- extract it in DDD, SSS
- 2d array
- if rc is 0, dealing with the registers, if rc is 1 youre dealing with the constants
- machine allows us to do ADD R0(src) R1(dst)
- if rc is 0, it means the source is a register R0. the destination is always a registers
- if we said ADD #1 R3, add 1 to r3. RC is 1 in this case. the src = 1
- fetch the inst
- extract first 3 bits
→ 0: BL
→ 1: cond
→ 2: bunch of stuf
→ 3: MOV
→ case 4
→ case 5
→ case 6
→ case 7
register initialization
- initialize by loading from memory
→ LD, LDR
→ Load: direct addressing, indexed
→ LDRelative: relative to another address
- or using immediate mode (use a constant)
→ MOV.
⇒ immediate
⇒ within CPU
- problems with immediate mode:
→ 16 bit fixed length instruction
→ instruction cannot refer to the next one, has to be in the instruction itself. how can you load a 16 bit value?
⇒ have to do it in steps because you only can use 8 bits of data at a time.
⇒ MOVL (move lo byte) low byte of data goes into low byte of register
⇒ MOVH (move high byte) high byte of data goes in high byte of register
⇒ 2 step operation
- initialize half the register at a time.
load and store
- load a value into a register and then access that location
→ LD R1, R2 == R2 ← mem[R1]
→ LD R0(src) R1(dst) == R1 ← mem{r0]
→ ST R2, R3 == mem[r3] ← r2
- indexed:
→ increment or decrement the register
→ Rx+ (post increment) (memory is accessed, then the register is incrmented)
→ Rx- (post decrement)
→ +Rx (r0 is incremented, and then the memory lcoation is accessed)
→ -Rx (pre increment and decrement)
→ use these to implement push and pull
→ push: store onto stack and then decrement stack pointer
→ pull: increment the stack pointer and load to memory
→ thsi is the reduced instruction set
⇒ if we want to push a register onto the stack:
⇒ ST R3 SP -
⇒ pull:
⇒ LD +SP R3
- relative:
→ using any register 0-7
→ signed seven-bit offset
⇒ extract offset
⇒ extend sign
⇒ add updated offset to register
Arithmetic/logic instructions
- d: destination
- s/c source register or constant
- w/b word or byte
- r/c source is either register or value
Index